Modern integrated circuit technology uses multiple layers of material to create an operational circuit. Successive layers of insulating, conducting, and semiconducting materials are patterned to form a structure that performs a specific function. The structure is typically linked with surrounding areas and subsequent layers. As known to those in the art, an integrated circuit is typically fabricated using a silicon substrate which can be selectively doped by diffusing impurities into the silicon to create active regions. Additional layers are located above the substrate to form a three dimensional circuit. These layers can be fabricated through numerous techniques, including deposition of semi-conductors or insulators, and growth of epitaxial layers. These layers are processed using photolithography, ion implantation, mask and etching processes, and other known techniques such as chemical-mechanical polishing (CMP) to form active and passive components.
To inter-connect the integrated circuit structures, and couple the components to external devices, one or more layers of metal are provided. These metal levels are generally referred to as metal-one and metal-two, in a two metal fabrication process. The metal-two layer is the uppermost metal level, and contains bonding pads for connection to external nodes. The lower metal layer does not contain bonding pads, as accessing this layer for bonding a wire would not be possible, or would require extra manufacturing steps.
Following patterning of the final metal level, a passivation layer is deposited over the entire top surface of the integrated circuit. This passivation layer is an insulating, protective layer that prevents mechanical and chemical damage during assembly in packaging of the integrated circuit. A probe pad and bonding contact mask is used to define patterns corresponding to areas in which electrical contact to the finished integrated circuit will be made. These patterns allow openings to be formed in the passivation layer for access to both bonding pads and probe pads.
During the development of an integrated circuit, it is often necessary to physically access internal nodes of the circuit to verify proper functionality of the circuitry, or to determine which circuitry has failed. It is also sometimes useful to force a voltage level on an internal node to check the behavior of circuitry affected by that node. Traditionally, external nodes are connected through large bond pads, typically square of 100 .mu.m side, on which a wire can be bonded. On earlier technologies, with lithography down to 1 .mu.m, it was possible to probe a metal line using mechanical devices with a very fine tip and fine position adjustments. With such devices, it was usually possible to put a probe tip on a one micron wide line, even though this requires a very careful set-up. This type of mechanical alignment is not possible with technologies which use smaller lithography. In these devices, nodes which are desired to be checked are identified and small probe pads are designed for fabrication in the integrated circuit. Such pads typically are at least 5 microns on a side. Including these probe pads can substantially affect the size of an integrated circuit. Thus, valuable integrated circuit real estate must be dedicated to fabricating probe pads. During the production of the integrated circuit, a majority of the probe pads are typically not necessary. That is, the probe pads are primarily useful during pre-production testing of the integrated circuit to verify improper operation of internal circuitry, and for troubleshooting defects identified during testing.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for testing integrated circuits during pre-production testing while minimizing integrated circuit real estate dedicated to probe pads during production. Further, there is a need in the art for an integrated circuit which provides access to internal nodes without increasing the production integrated circuit die area.